Version 4.1 SHEET 1 4060 2600 WIRE 1968 1744 1808 1744 WIRE 2208 1744 1968 1744 WIRE 1808 1760 1808 1744 WIRE 2208 1792 2208 1744 WIRE 2576 1792 2448 1792 WIRE 2992 1808 2752 1808 WIRE 2576 1824 2576 1792 WIRE 2992 1824 2992 1808 WIRE 1968 1840 1968 1744 WIRE 1808 1856 1808 1840 WIRE 2208 1888 2208 1872 WIRE 2304 1888 2208 1888 WIRE 2992 1920 2992 1904 WIRE 2992 1920 2800 1920 WIRE 2576 1936 2576 1904 WIRE 2640 1936 2576 1936 WIRE 2208 1952 2208 1888 WIRE 1968 2000 1968 1920 WIRE 2064 2000 1968 2000 WIRE 2144 2000 2064 2000 WIRE 2672 2000 2624 2000 WIRE 2752 2000 2752 1808 WIRE 2752 2000 2672 2000 WIRE 1648 2032 1392 2032 WIRE 1744 2032 1648 2032 WIRE 1968 2032 1968 2000 WIRE 1968 2032 1808 2032 WIRE 2800 2032 2800 1920 WIRE 2208 2080 2208 2048 WIRE 2288 2080 2208 2080 WIRE 2320 2080 2288 2080 WIRE 2448 2080 2448 1792 WIRE 2448 2080 2384 2080 WIRE 1392 2096 1392 2032 WIRE 2576 2128 2576 2032 WIRE 2800 2128 2800 2112 WIRE 1968 2144 1968 2032 WIRE 2208 2208 2208 2080 WIRE 1392 2304 1392 2176 WIRE 1968 2336 1968 2224 WIRE 2208 2336 2208 2288 FLAG 2208 2336 0 FLAG 1808 1856 0 FLAG 2304 1888 output FLAG 2576 2128 0 FLAG 2288 2080 emmitter FLAG 2064 2000 base FLAG 2672 2000 gate FLAG 2640 1936 drain FLAG 1648 2032 RF_input FLAG 1968 2336 0 FLAG 1392 2304 0 FLAG 2800 2128 0 SYMBOL NJF 2624 1936 M0 SYMATTR InstName Q1 SYMATTR Value 2N3819 SYMBOL RES 2192 1776 R0 SYMATTR InstName R1 SYMATTR Value 10k SYMBOL res 2192 2192 R0 SYMATTR InstName R2 SYMATTR Value 2k SYMBOL VOLTAGE 1808 1744 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value 12 SYMBOL npn 2144 1952 R0 SYMATTR InstName Q3 SYMATTR Value 2N2222 SYMBOL res 2560 1808 R0 SYMATTR InstName R3 SYMATTR Value 1R SYMBOL res 1952 2128 R0 SYMATTR InstName R4 SYMATTR Value 10k SYMBOL res 1952 1824 R0 SYMATTR InstName R5 SYMATTR Value 100k SYMBOL cap 1744 2048 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName C1 SYMATTR Value 1µ SYMBOL voltage 1392 2080 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 WINDOW 3 -88 111 Left 2 SYMATTR Value SINE(0 100m 100k) SYMATTR InstName V2 SYMBOL voltage 2992 1808 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V3 SYMATTR Value SINE(0 100m 1k) SYMBOL voltage 2800 2016 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 WINDOW 3 24 44 Left 2 SYMATTR Value -2.8V SYMATTR InstName V4 SYMBOL cap 2384 2064 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C2 SYMATTR Value 10µ TEXT 1144 1040 Left 5 ;Creating AM by varying the gain of an amplifier using a variable resistance FET. TEXT 1256 1384 Left 2 ;We start with the circuit "common emmitter-3"\nin the simpler circuits section,\nthen add the variable resistance FET circuit. TEXT 2536 1600 Left 4 ;The variable \nresistance\nFET circuit. TEXT 2928 1688 Left 4 ;Audio input signal TEXT 2672 2056 Left 2 ;DC bias\nfor FET. TEXT 2296 1920 Left 2 ;(collector) TEXT 1264 1656 Left 3 ;Local oscillator. TEXT 2496 1160 Left 4 ;Instructions TEXT 1840 1672 Left 4 ;Common emmitter amp TEXT 1264 1232 Left 2 ;This type of circuit will be usefull for AGC (automatic gain control),\nas part of a reciever.\nbut here its implementation is for AM.\nHowever this is not the most efficient way of creating AM,\nas any following amplifiers have to be linear. TEXT 1280 1176 Left 4 ;Circuit description TEXT 1464 2400 Left 2 !.tran 0 1 500m 100n TEXT 2504 1208 Left 2 ;click on run\nthen click on "RF_input" to plot it.\nthen click on the plot window then on plot settings / add plot pane\nthen click on "gate" to plot it\nthen click on the plot window and plot settings/add plot pane\nthen click on "output" to plot it\nlet the simulation finish then...\nzoom in on the "output" waveform to see the AM envelope at 1khz\nthen click on the plot window and view/FFT\nin the window that opens click on "output" then "okay"\nzoom in on the 100khz peak,\nit shows the AM carrier and sidebands. TEXT 2520 2296 Left 2 ;You may republish this circuit and text providing this line \nand the following lines are included.\nCircuit design by Keith Wallbanks.,\nOriginally released on analogsimulation.co.uk\nThis circuit is provided as is without warranty of any kind.\nThe intention of this text is to implement the MIT licence. TEXT 1240 2424 Left 1 ;You may republish or reuse this circuit implementation and text providing this line and the following lines are included.\nThis circuit implementation designed by Keith Wallbanks. Originally released on analogsimulation.co.uk\nThis circuit is provided as is without warranty of any kind. This text is intended to implement the MIT licence. RECTANGLE Normal 2896 2160 2512 1712 2 RECTANGLE Normal 2384 2368 1744 1712 2 RECTANGLE Normal 1552 2336 1232 1696 2 RECTANGLE Normal 3248 1984 2944 1712 2