Version 4.1 SHEET 1 2884 1232 WIRE 368 -448 336 -448 WIRE 480 -448 448 -448 WIRE 672 -448 544 -448 WIRE -784 -432 -816 -432 WIRE -512 -432 -784 -432 WIRE -384 -432 -432 -432 WIRE -256 -432 -384 -432 WIRE -176 -432 -256 -432 WIRE 64 -432 -176 -432 WIRE 64 -416 64 -432 WIRE -816 -368 -816 -432 WIRE -384 -368 -384 -432 WIRE -256 -368 -256 -432 WIRE 1360 -352 976 -352 WIRE 64 -304 64 -336 WIRE 128 -304 128 -336 WIRE 128 -304 64 -304 WIRE 176 -304 128 -304 WIRE 336 -304 336 -448 WIRE 336 -304 256 -304 WIRE 384 -304 336 -304 WIRE 976 -304 976 -352 WIRE 672 -288 672 -448 WIRE 672 -288 560 -288 WIRE 720 -288 672 -288 WIRE 1600 -272 1552 -272 WIRE 1728 -272 1600 -272 WIRE 64 -256 64 -304 WIRE 1552 -240 1552 -272 WIRE 560 -224 560 -288 WIRE 384 -208 336 -208 WIRE 336 -176 336 -208 WIRE -816 -96 -816 -288 WIRE -528 -96 -816 -96 WIRE -384 -96 -384 -304 WIRE -384 -96 -528 -96 WIRE -256 -96 -256 -288 WIRE -256 -96 -384 -96 WIRE 1552 -96 1552 -160 WIRE 64 -64 64 -176 WIRE 336 -64 336 -96 WIRE 336 -64 64 -64 WIRE 560 -64 560 -144 WIRE 560 -64 336 -64 WIRE 832 -64 560 -64 WIRE 976 -64 976 -224 WIRE 976 -64 832 -64 WIRE -528 -48 -528 -96 WIRE 832 0 832 -64 WIRE 432 368 400 368 WIRE 544 368 512 368 WIRE 736 368 608 368 WIRE -720 384 -752 384 WIRE -576 384 -720 384 WIRE -448 384 -496 384 WIRE -320 384 -448 384 WIRE -192 384 -320 384 WIRE -112 384 -192 384 WIRE 128 384 -112 384 WIRE 128 400 128 384 WIRE -752 448 -752 384 WIRE -448 448 -448 384 WIRE -192 448 -192 384 WIRE -320 464 -320 384 WIRE 1424 464 1040 464 WIRE 128 512 128 480 WIRE 192 512 192 480 WIRE 192 512 128 512 WIRE 240 512 192 512 WIRE 400 512 400 368 WIRE 400 512 320 512 WIRE 448 512 400 512 WIRE 1040 512 1040 464 WIRE 736 528 736 368 WIRE 736 528 624 528 WIRE 784 528 736 528 WIRE 1664 544 1616 544 WIRE 1792 544 1664 544 WIRE 128 560 128 512 WIRE 1616 576 1616 544 WIRE 624 592 624 528 WIRE -320 608 -320 544 WIRE 448 608 400 608 WIRE 400 640 400 608 WIRE -752 720 -752 528 WIRE -592 720 -752 720 WIRE -448 720 -448 512 WIRE -448 720 -592 720 WIRE -320 720 -320 672 WIRE -320 720 -448 720 WIRE -192 720 -192 528 WIRE -192 720 -320 720 WIRE 1616 720 1616 656 WIRE 128 752 128 640 WIRE 400 752 400 720 WIRE 400 752 128 752 WIRE 624 752 624 672 WIRE 624 752 400 752 WIRE 896 752 624 752 WIRE 1040 752 1040 592 WIRE 1040 752 896 752 WIRE -592 768 -592 720 WIRE 896 816 896 752 FLAG -176 -432 power_supply_output FLAG 832 0 0 FLAG -528 -48 0 FLAG -784 -432 Vin FLAG 720 -288 error FLAG 1360 -352 power_trafo_pri FLAG 128 -336 pot_divided FLAG 384 -304 inv FLAG 384 -208 non_inv FLAG 1600 -272 power_trafo_sec FLAG 1552 -96 0 FLAG -112 384 power_supply_output-1 FLAG 896 816 0 FLAG -592 768 0 FLAG -720 384 Vin-1 FLAG 784 528 error-1 FLAG 1424 464 power_trafo_pri-1 FLAG 192 480 pot_divided-1 FLAG 448 512 inv-1 FLAG 448 608 non_inv-1 FLAG 1664 544 power_trafo_sec-1 FLAG 1616 720 0 SYMBOL ind -416 -448 R90 WINDOW 0 5 56 VBottom 2 WINDOW 3 32 56 VTop 2 WINDOW 39 60 56 VTop 2 SYMATTR InstName L1 SYMATTR Value 100µ SYMATTR SpiceLine Rser=1m SYMBOL cap -400 -368 R0 WINDOW 39 -24 82 Left 2 SYMATTR SpiceLine Rser=20m SYMATTR InstName C1 SYMATTR Value 100µ SYMBOL res -272 -384 R0 SYMATTR InstName R1 SYMATTR Value 10R SYMBOL res 80 -432 M0 SYMATTR InstName R3 SYMATTR Value 14k SYMBOL res 80 -272 M0 SYMATTR InstName R4 SYMATTR Value 1k SYMBOL res 160 -320 M90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R5 SYMATTR Value 10k SYMBOL cap 480 -464 M90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C3 SYMATTR Value 220n SYMBOL res 352 -464 M90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R6 SYMATTR Value 10k SYMBOL voltage -816 -384 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V2 SYMATTR Value ac 1. SYMBOL bv 976 -320 M0 WINDOW 3 -90 113 Left 2 SYMATTR Value V=24.5*V(error) SYMATTR InstName B1 SYMBOL bv 560 -240 M0 WINDOW 3 -195 111 Left 2 SYMATTR Value V=1E6*(V(non_inv)-V(inv)) SYMATTR InstName B2 SYMBOL res 352 -192 M0 SYMATTR InstName R7 SYMATTR Value 1m SYMBOL bv 1552 -256 M0 WINDOW 3 -90 113 Left 2 SYMATTR Value V=0.5*V(power_trafo_pri) SYMATTR InstName B5 SYMBOL ind -480 368 R90 WINDOW 0 5 56 VBottom 2 WINDOW 3 32 56 VTop 2 WINDOW 39 60 56 VTop 2 SYMATTR InstName L2 SYMATTR Value 100µ SYMATTR SpiceLine Rser=1m SYMBOL cap -464 448 R0 WINDOW 39 -24 82 Left 2 SYMATTR SpiceLine Rser=20m SYMATTR InstName C2 SYMATTR Value 100µ SYMBOL res -208 432 R0 SYMATTR InstName R2 SYMATTR Value 10R SYMBOL res 144 384 M0 SYMATTR InstName R8 SYMATTR Value 14k SYMBOL res 144 544 M0 SYMATTR InstName R9 SYMATTR Value 1k SYMBOL res 224 496 M90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R10 SYMATTR Value 10k SYMBOL cap 544 352 M90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C4 SYMATTR Value 22n SYMBOL res 416 352 M90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R11 SYMATTR Value 10k SYMBOL voltage -752 432 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value ac 1. SYMBOL bv 1040 496 M0 WINDOW 3 -90 113 Left 2 SYMATTR Value V=24.5*V(error-1) SYMATTR InstName B3 SYMBOL bv 624 576 M0 WINDOW 3 -195 111 Left 2 SYMATTR Value V=1E6*(V(non_inv-1)-V(inv-1)) SYMATTR InstName B4 SYMBOL res 416 624 M0 SYMATTR InstName R12 SYMATTR Value 1m SYMBOL bv 1616 560 M0 WINDOW 3 -90 113 Left 2 SYMATTR Value V=0.5*V(power_trafo_pri-1) SYMATTR InstName B6 SYMBOL cap -336 608 R0 SYMATTR InstName C5 SYMATTR Value 330µ SYMBOL res -336 448 R0 SYMATTR InstName R13 SYMATTR Value 1R TEXT 728 -520 Left 2 ;this voltage gain of 49/2=24.5 is from\nthe input voltage divided by\nthe peak to peak sawtooth Voltage\nwe take half the input voltage as a half bridge\nonly puts half the input voltage\nacross the power tranformer primary. TEXT -464 -1328 Left 5 ;UC2875 full bridge, phase shift control, loop response, TEXT 664 888 Left 2 !.ac dec 100 10 100k TEXT -808 -1248 Left 2 ;firstly we have to add realistic ESR to the output capacitors, I have put this in as 20 m Ohms.\nthen running this sim as is shows two problems.\nthe peak in the response of the LC filter which could cause ringing or oscillations at 750hz\nrequires to be damped.\nthe loop does not have enough bandwidth, this will make the power supply respond slowly to transients, \nso the resulting output voltage transients will be larger and last longer. \nfor the damping \n...in parrallel with the output capacitor, add a larger capacitor with a resistor in series\nthe convention is to add 3 times the present value of C, \nthe additional R in series is the impedance of the inductor at the 1.6khz resonant freq, this is 1 Ohm.\nadding this has removed the peaky response of the LC filter.\nin order to increase the bandwidth of the control loop, in the error amp circuit, increase the output R and C impedances.\n \nNow check that hte control loop is stable, so that it won't oscillate or ring.\nthat is check what the phase is when the gain goes through 0db, this is called the phase margin, this should be at least 25 degrees.\nif the phase goes through zero then check how much below 0dbs the gain is at this point, this is called the phase margin.\nfor this example the phase margin is about 30 degrees.\nthere is no gain margin as the phase does not go through 0 degrees. TEXT -704 -568 Left 4 ;LC filter and load TEXT -80 -576 Left 4 ;potential divider and error amp TEXT 824 -648 Left 4 ;supply volts\n/p-p sawtooth Volts TEXT -96 -672 Left 5 ;Original control loop TEXT -144 48 Left 5 ;Improved control loop TEXT -640 248 Left 4 ;LC filter and load TEXT -16 240 Left 4 ;potential divider and error amp TEXT 912 232 Left 4 ;supply volts\n/p-p sawtooth Volts TEXT -464 56 Left 2 ;changes are\nadding the RC (capacitive damper) in parallel with the output cap.\nThe capacvitor around the error amp behaves as an integrator,\nincreasing low frequency gain, I have reduced the value of this capacitor to give more low freq gain\nand to make this gain continue out to a higher frequency, \nthis makes the power supply settle to its output voltage more quickly TEXT -800 856 Left 2 ;You may republish or reuse this circuit implementation and text providing this line and the following lines are included.\nThis circuit implementation designed by Keith Wallbanks. Originally released on analogsimulation.co.uk\nThis circuit is provided as is without warranty of any kind. This text is intended to implement the MIT licence. LINE Normal 512 -384 512 -384 2 LINE Normal 576 432 576 432 2 RECTANGLE Normal -160 0 -704 -544 2 RECTANGLE Normal 704 0 -16 -544 2 RECTANGLE Normal 1328 32 816 -544 2 RECTANGLE Normal -96 816 -640 272 2 RECTANGLE Normal 768 816 48 272 2 RECTANGLE Normal 1392 848 880 272 2