Version 4.1
SHEET 1 2388 1384
WIRE -1056 -272 -1088 -272
WIRE -928 -272 -1056 -272
WIRE -368 -272 -928 -272
WIRE -256 -272 -368 -272
WIRE 256 -272 -160 -272
WIRE 352 -272 256 -272
WIRE 400 -272 352 -272
WIRE 528 -272 480 -272
WIRE 576 -272 528 -272
WIRE 672 -272 576 -272
WIRE 800 -272 672 -272
WIRE 944 -272 800 -272
WIRE 1344 -272 944 -272
WIRE -1088 -208 -1088 -272
WIRE -368 -208 -368 -272
WIRE 528 -208 528 -272
WIRE 800 -208 800 -272
WIRE 944 -192 944 -272
WIRE 672 -176 672 -272
WIRE 352 -144 352 -272
WIRE 432 -144 352 -144
WIRE -240 -128 -240 -224
WIRE 352 -128 352 -144
WIRE 432 -112 432 -144
WIRE -368 -80 -368 -128
WIRE -240 -80 -240 -128
WIRE -240 -80 -368 -80
WIRE -368 -48 -368 -80
WIRE 672 -16 672 -96
WIRE 432 16 432 -32
WIRE 432 64 432 16
WIRE -368 80 -368 32
WIRE -368 80 -848 80
WIRE -1088 160 -1088 -128
WIRE 352 160 352 -64
WIRE 352 160 -1088 160
WIRE 384 160 352 160
WIRE 432 160 432 128
WIRE 432 160 384 160
WIRE 528 160 528 -144
WIRE 528 160 432 160
WIRE 672 160 672 48
WIRE 672 160 528 160
WIRE 800 160 800 -128
WIRE 800 160 672 160
WIRE 944 160 944 -112
WIRE 944 160 800 160
WIRE 384 208 384 160
WIRE -928 352 -928 -272
WIRE -736 352 -928 352
WIRE -656 352 -736 352
WIRE -192 352 -544 352
WIRE 864 352 -192 352
WIRE -544 384 -544 352
WIRE 976 432 480 432
WIRE 1040 432 976 432
WIRE 1136 432 1104 432
WIRE 1232 432 1216 432
WIRE 1344 464 1344 -272
WIRE -544 512 -544 464
WIRE 1232 512 1232 432
WIRE 1232 512 1072 512
WIRE 1072 576 1072 512
WIRE 1152 576 1072 576
WIRE 1344 576 1344 544
WIRE 1344 576 1232 576
WIRE -848 608 -848 80
WIRE -736 608 -848 608
WIRE -656 608 -736 608
WIRE 1344 624 1344 576
WIRE -192 640 -192 352
WIRE -192 640 -208 640
WIRE 864 656 864 352
WIRE -656 672 -656 608
WIRE 1008 672 896 672
WIRE 1072 672 1072 576
WIRE 1072 672 1008 672
WIRE -208 688 -208 640
WIRE -192 688 -192 640
WIRE 272 688 256 688
WIRE 352 688 272 688
WIRE 480 688 480 432
WIRE 480 688 432 688
WIRE 832 688 480 688
WIRE -48 704 -160 704
WIRE 944 704 896 704
WIRE -544 720 -592 720
WIRE -384 720 -464 720
WIRE -224 720 -384 720
WIRE 256 736 -160 736
WIRE -48 752 -48 704
WIRE 944 752 944 704
WIRE 944 752 672 752
WIRE 592 768 528 768
WIRE 944 768 944 752
WIRE -208 784 -208 752
WIRE -192 784 -192 752
WIRE -192 784 -208 784
WIRE -176 784 -176 752
WIRE -176 784 -192 784
WIRE -144 784 -176 784
WIRE 528 784 528 768
WIRE 256 800 256 736
WIRE -736 912 -816 912
WIRE -656 912 -656 768
WIRE -656 912 -736 912
WIRE -144 912 -144 784
WIRE -144 912 -656 912
WIRE -48 912 -48 832
WIRE -48 912 -144 912
WIRE 256 912 256 880
WIRE 256 912 -48 912
WIRE 592 912 592 768
WIRE 592 912 256 912
WIRE 864 912 864 720
WIRE 864 912 592 912
WIRE 944 912 944 848
WIRE 944 912 864 912
WIRE 1344 944 1344 704
WIRE 528 976 528 864
WIRE 672 976 672 752
WIRE 528 1040 528 976
WIRE 528 1040 432 1040
WIRE 432 1056 432 1040
WIRE 672 1072 672 976
WIRE 528 1088 528 1040
WIRE -816 1168 -816 912
WIRE 432 1168 432 1136
WIRE 432 1168 -816 1168
WIRE 528 1168 528 1152
WIRE 528 1168 432 1168
WIRE 672 1168 672 1152
WIRE 672 1168 528 1168
WIRE 672 1200 672 1168
FLAG 256 -272 drain
FLAG 576 -272 output
FLAG -384 720 PWM
FLAG 384 208 0
FLAG 272 688 Verror
FLAG -1056 -272 Vin
FLAG -736 352 2_Vin
FLAG -736 608 1_Vo
FLAG -736 912 8_gnd
FLAG 976 432 3_comp
FLAG 1008 672 4_FB
FLAG 1344 944 0
FLAG 432 16 snub
FLAG -240 -128 gate
FLAG 672 976 7_RT
FLAG 672 1200 0
FLAG 528 976 6_DTC
FLAG -544 512 0
SYMBOL ind 496 -288 R90
WINDOW 0 5 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 39 60 56 VTop 2
SYMATTR InstName L1
SYMATTR Value 47µ
SYMATTR SpiceLine Rser=1m
SYMBOL cap 512 -208 R0
WINDOW 39 -13 83 Left 2
SYMATTR SpiceLine Rser=20m
SYMATTR InstName C1
SYMATTR Value 1m
SYMBOL res 784 -224 R0
SYMATTR InstName R1
SYMATTR Value 5R
SYMBOL diode 368 -64 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value MBR20100CT
SYMBOL current 944 -192 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName I1
SYMATTR Value PULSE(0 1 1200m 0.1m 0.1m 100m 1)
SYMBOL voltage 944 752 R0
SYMATTR InstName V3
SYMATTR Value 1V
SYMBOL res 1328 448 R0
SYMATTR InstName R3
SYMATTR Value 8k
SYMBOL res 1328 608 R0
SYMATTR InstName R4
SYMATTR Value 2k
SYMBOL res 1248 560 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 10k
SYMBOL cap 1104 416 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 4.7n
SYMBOL res 1232 416 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R6
SYMATTR Value 100k
SYMBOL voltage -48 736 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 -143 102 Left 2
SYMATTR Value PULSE(0.7 1.3 0 4.9u 4.9u 0.1u 10u)
SYMATTR InstName V4
SYMBOL voltage -1088 -224 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 10 1u 1m 1m 10 20)
SYMBOL res -384 -224 R0
SYMATTR InstName R8
SYMATTR Value 470R
SYMBOL npn -592 672 M0
SYMATTR InstName Q1
SYMATTR Value 2N2222
SYMBOL res 448 672 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R9
SYMATTR Value 1R
SYMBOL res -384 -64 R0
WINDOW 0 51 36 Left 2
SYMATTR InstName R10
SYMATTR Value 470R
SYMBOL res 416 -128 R0
SYMATTR InstName R11
SYMATTR Value 200R
SYMBOL cap 416 64 R0
SYMATTR InstName C5
SYMATTR Value 10n
SYMBOL OpAmps\\UniversalOpAmp2 864 688 M0
WINDOW 123 -137 50 Left 2
SYMATTR InstName U1
SYMBOL Comparators\\LT1719 -192 656 M0
SYMATTR InstName U2
SYMBOL res -448 704 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL nmos -160 -224 M270
SYMATTR InstName X1
SYMATTR Value RD3L01BAT
SYMATTR Prefix X
SYMBOL cap 656 -16 R0
SYMATTR InstName C2
SYMATTR Value 3m
SYMBOL res 656 -192 R0
SYMATTR InstName R7
SYMATTR Value 0.2R
SYMBOL res 656 1056 R0
SYMATTR InstName R_RT
SYMATTR Value 100k
SYMBOL bi 528 784 R0
SYMATTR InstName B2
SYMATTR Value I=I(R_RT)
SYMBOL cap 512 1088 R0
SYMATTR InstName C_softstart
SYMATTR Value 1µ
SYMBOL res 416 1040 R0
SYMATTR InstName R12
SYMATTR Value 200k
SYMBOL bv 256 784 R0
WINDOW 3 -101 98 Left 2
SYMATTR Value V=min(V(Verror), V(6_DTC))
SYMATTR InstName B3
SYMBOL bv -544 368 R0
SYMATTR InstName B4
SYMATTR Value V=limit(0V,V(2_Vin),2.2V)
TEXT -1008 1064 Left 2 !.tran 0 500m 0 100n
TEXT 152 -648 Left 5 ;simple buck, TL5001a\nTI also make the LM5155 which is \nsimilar functionality but different pin out.
TEXT -16 280 Left 2 ;TL5001 (control IC)
TEXT -1152 -664 Left 2 ;the TL5001 control IC is chosen as it uses external FET and diode, \nthis makes the circuit more flexible.\nit is also relatively simple to aid understanding.\nand it has been around for decades so is likely to continue to exist.\n \nThe model of the TL5001 used here is my own creation, it may not precisely reflect reality in all areas,\nthe purpose is to enable you to see the internal waveforms.\nThe FET is Pchannel as this makes the drive circuit simpler.\nNchannel FETs give better performance but would require a gate drive Voltage above the supply rail voltage.\nthe FET is rated to 60V and the diode 100V\nthe FEt and the diode are both rated to 10A, \nhowever care must be taken that they don't overheat.
TEXT 1432 -576 Left 2 !* RD3L01BAT PMOSFET model\n* Model Generated by ROHM\n* All Rights Reserved\n* Commercial Use or\n* Resale Restricted\n* Date: 2021/06/02\n******************D G S\n.SUBCKT RD3L01BAT 1 2 3\nM1 11 22 3 3 MOS_P\nD1 1 3 DDS1\nR1 1 11 RTH 61.536E-3\nRG 2 22 39.82\nD14 11 22 DGD1\n.MODEL MOS_P PMOS TNOM = 25\n+ LEVEL = 3\n+ L = 2.0000E-6\n+ W = 1\n+ KP = 73.699E-6\n+ RS = 0\n+ RD = 0\n+ VTO = -2.078\n+ TOX = 2.0000E-6\n+ CGSO = 1000.0E-12\n+ CGDO = 0\n+ CBD = 1.0000E-15\n+ N = 2\n+ GAMMA = 0.8\n+ ETA = 0\n+ KAPPA = 1\n+ NFS = 14.000E+9\n+ XJ = 1.0000E-6\n+ UO = 247.91\n+ VMAX = 50.000E+3\n.MODEL DDS1 D TNOM = 25\n+ IS = 6.7392E-12\n+ N = 1.0781\n+ RS = 14.833E-3\n+ IKF = 0.9031\n+ CJO = 486.00E-12\n+ M = 0.6865\n+ VJ = 0.8694\n+ XTI = 5.9994\n+ BV = 60\n+ TT = 21.000E-9\n.MODEL RTH RES TNOM = 25\n+ TC1 = 3.8327E-3\n+ TC2 = 6.3382E-6\n.MODEL DGD1 D TNOM = 25\n+ N = 10.000E+3\n+ CJO = 140.00E-12\n+ M = 0.2625\n+ VJ = 10.955\n+ FC = 0.05\n+ T_ABS = 25\n.ENDS
TEXT -1000 1104 Left 2 !.ic V(6_DTC)=0V
TEXT -640 264 Left 2 ;B4 functions \nas a 2.2V\nlinear reg
TEXT 128 600 Left 2 ;B3 turns U2 into a \ndual ip comparator
TEXT 824 1024 Left 2 ;you can reduce C_softstart \nthis will make the startup faster\nbut it will also increase the \noutput voltage overshoot on startup
TEXT -880 1192 Left 2 ;the frequency of this simulation is fixed at 100khz \nand is not dependent on the value of R_RT\nthe real TL5001A sets its freq depending on the value of R_RT\n \nthis simulation does not reflect the current limit or the duty cycle limit\nof the real TL5001A
TEXT 336 1240 Left 1 ;You may republish or reuse this circuit implementation and text providing this line and the following lines are included.\nThis circuit implementation designed by Keith Wallbanks. Originally released on analogsimulation.co.uk\nThis circuit is provided as is without warranty of any kind. This text is intended to implement the MIT licence.
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LINE Normal -48 560 -48 560 2
RECTANGLE Normal -752 1024 -736 1024 2
RECTANGLE Normal -768 1072 -752 1072 2
RECTANGLE Normal 1008 256 -736 960 2