Version 4.1 SHEET 1 6300 4404 WIRE 240 -48 144 -48 WIRE 432 -48 320 -48 WIRE 464 -48 432 -48 WIRE -752 -16 -848 -16 WIRE -608 -16 -752 -16 WIRE 144 -16 144 -48 WIRE -848 0 -848 -16 WIRE -848 96 -848 80 WIRE -656 96 -672 96 WIRE -608 96 -608 -16 WIRE -608 96 -656 96 WIRE -672 128 -672 96 WIRE -656 128 -656 96 WIRE 144 128 144 64 WIRE -704 144 -800 144 WIRE 464 144 464 -48 WIRE -512 160 -640 160 WIRE -192 160 -512 160 WIRE -704 176 -736 176 WIRE -192 176 -272 176 WIRE 16 176 -128 176 WIRE -192 192 -224 192 WIRE -224 208 -224 192 WIRE -192 208 -224 208 WIRE -800 224 -800 144 WIRE -688 224 -688 192 WIRE -688 224 -800 224 WIRE -672 224 -672 192 WIRE -672 224 -688 224 WIRE -656 224 -656 192 WIRE -656 224 -672 224 WIRE -512 224 -512 160 WIRE -464 224 -512 224 WIRE -336 224 -384 224 WIRE -288 224 -336 224 WIRE -272 224 -272 176 WIRE -272 224 -288 224 WIRE -224 224 -224 208 WIRE -192 224 -224 224 WIRE -224 240 -224 224 WIRE -208 240 -224 240 WIRE -176 240 -176 224 WIRE -176 240 -208 240 WIRE -336 256 -336 224 WIRE -208 256 -208 240 WIRE 288 256 224 256 WIRE 400 256 400 208 WIRE 400 256 368 256 WIRE 416 256 400 256 WIRE -896 272 -1088 272 WIRE -736 272 -736 176 WIRE -736 272 -896 272 WIRE 464 272 464 224 WIRE 224 288 224 256 WIRE -1088 304 -1088 272 WIRE 528 320 464 320 WIRE -656 336 -672 336 WIRE -608 336 -608 96 WIRE -608 336 -656 336 WIRE -336 336 -336 320 WIRE -672 352 -672 336 WIRE -656 352 -656 336 WIRE 400 352 400 256 WIRE 416 352 400 352 WIRE -736 368 -736 272 WIRE -704 368 -736 368 WIRE -528 384 -640 384 WIRE -512 384 -528 384 WIRE -192 384 -512 384 WIRE -800 400 -800 224 WIRE -704 400 -800 400 WIRE -192 400 -272 400 WIRE 0 400 -128 400 WIRE 224 400 224 368 WIRE 464 400 464 368 WIRE 464 400 224 400 WIRE -1088 416 -1088 384 WIRE -192 416 -224 416 WIRE 464 416 464 400 WIRE 528 416 528 320 WIRE 528 416 464 416 WIRE -224 432 -224 416 WIRE -192 432 -224 432 WIRE -688 448 -688 416 WIRE -672 448 -672 416 WIRE -672 448 -688 448 WIRE -656 448 -656 416 WIRE -656 448 -672 448 WIRE -224 448 -224 432 WIRE -192 448 -224 448 WIRE -224 464 -224 448 WIRE -208 464 -224 464 WIRE -176 464 -176 448 WIRE -176 464 -208 464 WIRE -800 480 -800 400 WIRE -672 480 -672 448 WIRE -672 480 -800 480 WIRE -208 480 -208 464 WIRE -800 496 -800 480 WIRE -528 496 -528 384 WIRE -448 496 -528 496 WIRE -336 496 -368 496 WIRE -288 496 -336 496 WIRE -272 496 -272 400 WIRE -272 496 -288 496 WIRE -336 528 -336 496 WIRE 464 544 464 416 WIRE 528 544 464 544 WIRE 656 544 528 544 WIRE 832 544 736 544 WIRE 1104 544 832 544 WIRE 1264 544 1184 544 WIRE -336 608 -336 592 WIRE 1264 608 1264 544 WIRE 1264 608 1200 608 WIRE 464 672 464 544 WIRE 768 672 464 672 WIRE 1264 688 1264 608 WIRE 768 720 768 672 WIRE 464 736 464 672 WIRE 1264 784 1264 752 WIRE 1264 784 1200 784 WIRE 1600 800 1600 752 WIRE 1600 800 1568 800 WIRE 1616 800 1600 800 WIRE 1264 816 1264 784 WIRE 1264 816 1184 816 WIRE 1184 832 1184 816 WIRE 1264 832 1264 816 WIRE 1344 832 1264 832 WIRE 1568 832 1568 800 WIRE 1568 832 1440 832 WIRE 1616 832 1616 800 WIRE 304 848 240 848 WIRE 400 848 400 816 WIRE 400 848 384 848 WIRE 416 848 400 848 WIRE 768 848 768 800 WIRE 240 880 240 848 WIRE 464 880 464 816 WIRE 1344 912 1264 912 WIRE 1568 912 1440 912 WIRE 560 928 464 928 WIRE 1184 944 1184 912 WIRE 1264 944 1264 912 WIRE 1264 944 1184 944 WIRE 400 960 400 848 WIRE 416 960 400 960 WIRE 1568 960 1568 912 WIRE 1600 960 1568 960 WIRE 1616 960 1616 912 WIRE 1616 960 1600 960 WIRE 1600 992 1600 960 WIRE 240 1008 240 960 WIRE 464 1008 464 976 WIRE 464 1008 240 1008 WIRE 464 1024 464 1008 WIRE 560 1024 560 928 WIRE 560 1024 464 1024 WIRE 464 1056 464 1024 WIRE 544 1056 464 1056 WIRE 768 1056 768 912 WIRE 768 1056 544 1056 WIRE 1264 1056 1264 944 WIRE 1264 1056 768 1056 WIRE 544 1120 544 1056 FLAG 144 128 0 FLAG 544 1120 0 FLAG 432 -48 V_supply FLAG 1200 608 Cres FLAG 528 544 FET_center FLAG 832 544 Lres FLAG -800 496 0 FLAG -848 96 0 FLAG -752 -16 5V FLAG -512 160 2 FLAG -512 384 3 FLAG 400 208 upper_gate FLAG 400 816 lower_gate FLAG -896 272 test FLAG -336 336 0 FLAG -336 608 0 FLAG -208 256 0 FLAG -208 480 0 FLAG -288 224 2_delay FLAG -288 496 3_delay FLAG 16 176 hi_drive FLAG 0 400 lo_drive FLAG -1088 416 0 FLAG 1200 784 V_R_Load_pri FLAG 1600 992 0 FLAG 1600 752 V_R_Load SYMBOL bv 224 272 R0 SYMATTR InstName B8 SYMATTR Value V=3*V(hi_drive)-2 SYMBOL bv 240 864 R0 SYMATTR InstName B9 SYMATTR Value V=3*V(lo_drive)-2 SYMBOL res 384 240 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R3 SYMATTR Value 2R SYMBOL res 400 832 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R4 SYMATTR Value 2R SYMBOL voltage 144 -32 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V6 SYMATTR Value PULSE(0 390 1u 20u 1 10 20) SYMBOL res 224 -64 M90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R_in_sense SYMATTR Value 1m SYMBOL res 448 128 R0 SYMATTR InstName RS1 SYMATTR Value 1m SYMBOL res 448 720 R0 SYMATTR InstName RS2 SYMATTR Value 1m SYMBOL res 1088 528 M90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName Rpri_sense SYMATTR Value 1m SYMBOL ind 640 528 M90 WINDOW 0 5 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName L_res SYMATTR Value 1.25µ SYMATTR SpiceLine Rser=1m SYMBOL cap 752 848 R0 SYMATTR InstName C6 SYMATTR Value 10p SYMBOL res 752 704 R0 SYMATTR InstName R15 SYMATTR Value 2R SYMBOL res 1600 816 R0 SYMATTR InstName R_Load SYMATTR Value 50R SYMBOL cap 1280 752 R180 WINDOW 0 24 56 Left 2 WINDOW 3 24 8 Left 2 SYMATTR InstName C_res SYMATTR Value 0.12nF SYMBOL Comparators\\LT1719 -672 96 R0 SYMATTR InstName U1 SYMBOL Comparators\\LT1719 -672 320 R0 SYMATTR InstName U2 SYMBOL voltage -848 -16 R0 SYMATTR InstName V1 SYMATTR Value 5V SYMBOL res -368 208 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R2 SYMATTR Value 100R SYMBOL res -352 480 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R5 SYMATTR Value 100R SYMBOL cap -352 256 R0 SYMATTR InstName C3 SYMATTR Value 100p SYMBOL cap -352 528 R0 SYMATTR InstName C5 SYMATTR Value 100p SYMBOL Digital\\and -160 128 R0 WINDOW 3 -65 0 Left 2 WINDOW 123 16 52 Left 2 SYMATTR Value Vhigh=5 SYMATTR Value2 Trise=2n SYMATTR InstName A1 SYMBOL Digital\\and -160 352 R0 WINDOW 3 -55 -2 Left 2 WINDOW 123 16 52 Left 2 SYMATTR Value Vhigh=5 SYMATTR Value2 Trise=2n SYMATTR InstName A3 SYMBOL voltage -1088 288 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V3 SYMATTR Value SINE(0 1 14E6) SYMBOL ind 1328 816 R0 SYMATTR InstName L1 SYMATTR Value 10m SYMATTR Type ind SYMATTR SpiceLine Rser=1m SYMBOL ind 1424 816 R0 SYMATTR InstName L2 SYMATTR Value 26m SYMATTR Type ind SYMATTR SpiceLine Rser=1m SYMBOL res 1200 928 R180 WINDOW 0 36 76 Left 2 WINDOW 3 36 40 Left 2 SYMATTR InstName R1000 SYMATTR Value 100Meg SYMBOL nmos4 416 272 R0 SYMATTR InstName X1 SYMATTR Value IMBG65R260M1H_L0 SYMATTR Prefix X SYMBOL nmos4 416 880 R0 SYMATTR InstName X2 SYMATTR Value IMBG65R260M1H_L0 SYMATTR Prefix X TEXT -1184 712 Left 2 !.model pwr_diode D(Ron=1m Roff=1Meg Vfwd=.4) TEXT -1168 672 Left 2 !.tran 0 75u 25u 1n TEXT -1184 776 Left 2 !.model Sw_kw1 SW(Ron=.01 Roff=100Meg Vt=4 Vh=-1) TEXT 1336 784 Left 2 !k1 L1 L2 1 TEXT 1328 560 Left 3 ;power \ntransformer TEXT 1320 648 Left 2 ;turns ratio is 1.6\nor 5:8\nso inductance \nratio is 1:2.6 TEXT 976 1080 Left 2 ;the resistance that appears at the transformer primary \nis R_Load/ turns ratio squared,\n= 50/2.6 = 19 Ohms TEXT 552 432 Left 2 ;with 14Mhz and 120pF \nL would be 1.08uH for resonance\nL increased to 1.25uH to cause reduced loss switching TEXT 992 664 Left 2 ;0.94n, is 2 x 0.47n TEXT 1720 -552 Left 2 !.SUBCKT IMBG65R260M1H_L0 drain gate source source_k PARAMS: Ls=5.90E-09 Ld=2.58E-10 Lg=8.75E-09 Lssk=5.03E-09\n.PARAM fpar128=1.12E+00 fpar129=1.01E+00 Rs=1.52E-02 Rg=4.53E-02 Rssk=3.90E-02 fpar127=0.763\nLd drain dd {Ld}\nLg gate g {Lg}\nLs source s {Ls}\nRd drain dd 1.0\nRg gate g 1.0\nRs source s 1.0\nRssk source_k sk1 {Rssk}\nLssk sk1 s {Lssk}\nRsskcon source_k sk1 1.0\nX1 dd g s tech_sicmos_L0 PARAMS: Rs={Rs} Rg={Rg} fpar128={fpar128} fpar129={fpar129} fpar127={fpar127}\n.ENDS IMBG65R260M1H_L0 TEXT 1752 -136 Left 2 !************************ L0 TECHNOLOGY MODEL *************************\n**********************************************************************\n \n.SUBCKT tech_sicmos_L0 dd g s PARAMS: Rs=1 Rg=1 fpar128=1 fpar129=1 fpar127=1\n.PARAM fpar130={fpar128*fpar127/8.15}\n.PARAM fpar131={fpar129*fpar127/8.15}\n.PARAM Rd={15.3m/fpar130} Rd_TC1=-0.5m Rd_TC2=30.0u Rx=1m\n.PARAM DMOS_Vth=7.5 DMOS_KP={fpar130*25.1} DMOS_THETA=0 DMOS_VMAX=1.5e5 DMOS_ETA=0\n.PARAM DMOS_GAMMA=0 DMOS_IS={fpar130*1E-38} DMOS_T_ABS=150 DMOS_RS=0 DMOS_RB={0.01/fpar130}\n.PARAM MVDR_KP={fpar130*245} MVDR_Vth=-1 MVDR_LAMBDA=0.5\n.PARAM Cds1={fpar131*48p} Cox={fpar131*0.5n} Cgs={fpar131*2.1n}\n.PARAM sw_Vth=0.0 sw_KP=10\n.PARAM Dbt_BV=715 Dbt_M=0.53 Dbt_CJO={fpar131*2.31n} Dbt_VJ=2.4 Dbt_IS=1E-20 Dbt_N=20 Dbt_T_ABS=27\n.PARAM DGD_M=0.6 DGD_CJO={fpar131*0.5n} DGD_VJ=1.2 DGD_IS=1E-20 DGD_T_ABS=27\n.PARAM Eaux=1 Eaux2=-1\n.PARAM RDIBL1=500G RDIBL2=3G Rconv1=1Meg Rconv2=10Meg\n.MODEL DMOS NMOS(GAMMA={DMOS_GAMMA} IS={DMOS_IS} T_ABS={DMOS_T_ABS} RS={DMOS_RS} RB={DMOS_RB}\n+KP={DMOS_KP} VTO={DMOS_Vth}\n+ THETA={DMOS_THETA} VMAX={DMOS_VMAX} ETA={DMOS_ETA} LEVEL=3)\n.MODEL MVDR NMOS(KP={MVDR_KP} VTO={MVDR_Vth} LAMBDA={MVDR_LAMBDA} LEVEL=1)\n.MODEL sw NMOS(VTO={sw_Vth} KP={sw_KP} LEVEL=1)\n.MODEL Dbt D(IS={Dbt_IS} BV={Dbt_BV} M={Dbt_M} CJO={Dbt_CJO} VJ={Dbt_VJ} N={Dbt_N} T_ABS={Dbt_T_ABS} LEVEL=1)\n.MODEL DGD D(IS={DGD_IS} M={DGD_M} CJO={DGD_CJO} VJ={DGD_VJ} T_ABS={DGD_T_ABS} LEVEL=1)\nRs s s2 {Rs}\nRg g g2 {Rg}\nRd d2 d1a {Rd} TC1={Rd_TC1} TC2={Rd_TC2}\nM1 d2 g3 s2 s2 DMOS L={1u} W={1u}\nMr dd d2a d1a d1a MVDR L={1u} W={1u}\nRx d2a d1a {Rx}\nCds1 s2 d2 {Cds1}\nDbd s2 d2 Dbt\nMaux g2 c a a sw\nMaux2 b d g2 g2 sw\nEaux c a d2 g2 {Eaux}\nEaux2 d g2 d2 g2 {Eaux2}\nCox b d2 {Cox}\nRpar b d2 {Rconv1}\nDgd a d2 DGD\nRpar2 d2 a {Rconv2}\nCgs g2 s2 {Cgs}\nRDIBL1 d2 m1 {RDIBL1}\nRDIBL2 m1 s2 {RDIBL2}\nEinv m2 s2 m1 s2 {-1}\nEdibl g3 s2 g2 m2 {1}\n.ENDS\n \n********************************************************************** TEXT -1104 1080 Left 2 ;You may republish or reuse this circuit implementation and text providing this line and the following lines are included.\nThis circuit implementation designed by Keith Wallbanks. Originally released on analogsimulation.co.uk\nThis circuit is provided as is without warranty of any kind. This text is intended to implement the MIT licence. TEXT -536 -1424 Left 5 ;Fixed frequency Class D amplifier, Silicon Carbide FET, 14Mhz, supply Volts = 390V, max power a bit less than 1kW. TEXT 1728 -712 Left 2 ;The below is one of Infineons Spice models for this FET. Other Spice models for this FET exist on the Infineon website.\nWe are using Infineons gen1_low_tech_model, \nInfineon gen1 hi tech models are complex, \nI have not been able to get gen2 FET models to work. TEXT -928 -736 Left 2 ;click on run\nthen click on "2_out" to plot its Voltage\nthen click on "3_out" to plot its Voltage \nZoom in on the time axis to see the individual pulses.\nthese signals turn on the upper FET then the lower FET, one at a time.\nclick on the plot window, then on plot settings/add plot pane.\nthen click on "FET_center" to plot its Voltage\n \nclick on the plot window, then on plot settings/add plot pane.\nthen click on "V_R_Load_pri" to plot its voltage\nnote that "FET_center" was a square wave, and that "V_R_Load_pri" is a sine wave.\nL_res and C_res resonate the frequency that we are driving the FETs at.\n \nthen click on "V_R_Load" to plot its Voltage.\nthe transformer has a turns ratio of 1:3, so "V_R_Load" is 3 times "V_R_Load_pri".\nclick on the plot window, then on plot settings/add plot pane.\nclick on the circuit, press and hold the alt key, hover the mouse over R_Load and click.\nthis will plot the power out.\npress and hold the CTRL key, in the graph window click on "V(V_R_Load)*I(R_Load)"\na window will appear giving average power out.\n \nclick on the plot window, then on "View /FFT" in the top toolbar, then on "V(v-r_load)"\nthis will plot its FFT. TEXT -920 -816 Left 4 ;Instructions, first level TEXT 200 -808 Left 4 ;Instructions, reducing switching losses. TEXT -872 -1224 Left 4 ;A lower current rating FET is chosen, to keep FET output capacitance low, \nso that fast switching is possible.\nHowever the FET should still be adequately derated.\nAt 14Mhz the inductor will be air cored TEXT 224 -768 Left 2 ;resonance occurs at the 14Mhz driving frequency when\nC_res = 120pF and L_res = 1.08uH,\n \nHowever, if we operate at resonance we get lossy switching of the FETs, \nwe can reduce these switching losses by causing the resonant circuits current to charge\nthe FETs output capacitance during the "deadtime",in practice this means increasing \nthe value of the resonant inductor to 1.25uH.\nThis is explained in more detail in "reducing switching loss in a class D amplifier".\n \na couple of details here.\nThe efficiency figures here ignore several losses such as those in the inductor and transformer.\nHence you will not achieve such high efficiency in a real circuit.\nnote that the LTspice power dissipation function (achieved by pressing the alt key and hovering \nthe mouse over the component),\ndoes not function well for a complex component such as a FET. It works okay for a resistor though. TEXT 208 -320 Left 2 ;At resonance efficiency calculated as.... (power in R_load) / (390V x I(R_sense_in))\n= 844W out / (390V x 2.393A) input = 844W / 932W = 90.5%\n \nIncreased inductor value, efficiency calculated as.... (power in R_load) / (390V x I(R_sense_in))\n= 885.6W out / (390V x 2.422A) input = 885.6W / 944.6W = 93.8% RECTANGLE Normal 1536 944 1296 576 2