Version 4.1 SHEET 1 5276 4404 WIRE -864 144 -960 144 WIRE -720 144 -864 144 WIRE -960 160 -960 144 WIRE -960 256 -960 240 WIRE -768 256 -784 256 WIRE -720 256 -720 144 WIRE -720 256 -768 256 WIRE -784 288 -784 256 WIRE -768 288 -768 256 WIRE -816 304 -912 304 WIRE -624 320 -752 320 WIRE -304 320 -624 320 WIRE -816 336 -848 336 WIRE -304 336 -384 336 WIRE -96 336 -240 336 WIRE -304 352 -336 352 WIRE 304 352 208 352 WIRE 496 352 384 352 WIRE 528 352 496 352 WIRE -336 368 -336 352 WIRE -304 368 -336 368 WIRE -912 384 -912 304 WIRE -800 384 -800 352 WIRE -800 384 -912 384 WIRE -784 384 -784 352 WIRE -784 384 -800 384 WIRE -768 384 -768 352 WIRE -768 384 -784 384 WIRE -624 384 -624 320 WIRE -576 384 -624 384 WIRE -448 384 -496 384 WIRE -400 384 -448 384 WIRE -384 384 -384 336 WIRE -384 384 -400 384 WIRE -336 384 -336 368 WIRE -304 384 -336 384 WIRE 208 384 208 352 WIRE -336 400 -336 384 WIRE -320 400 -336 400 WIRE -288 400 -288 384 WIRE -288 400 -320 400 WIRE -448 416 -448 384 WIRE -320 416 -320 400 WIRE -1008 432 -1200 432 WIRE -848 432 -848 336 WIRE -848 432 -1008 432 WIRE -1200 464 -1200 432 WIRE -768 496 -784 496 WIRE -720 496 -720 256 WIRE -720 496 -768 496 WIRE -448 496 -448 480 WIRE -784 512 -784 496 WIRE -768 512 -768 496 WIRE -848 528 -848 432 WIRE -816 528 -848 528 WIRE 208 528 208 464 WIRE -640 544 -752 544 WIRE -624 544 -640 544 WIRE -304 544 -624 544 WIRE 528 544 528 352 WIRE -912 560 -912 384 WIRE -816 560 -912 560 WIRE -304 560 -384 560 WIRE -112 560 -240 560 WIRE -1200 576 -1200 544 WIRE -304 576 -336 576 WIRE -336 592 -336 576 WIRE -304 592 -336 592 WIRE -800 608 -800 576 WIRE -784 608 -784 576 WIRE -784 608 -800 608 WIRE -768 608 -768 576 WIRE -768 608 -784 608 WIRE -336 608 -336 592 WIRE -304 608 -336 608 WIRE -336 624 -336 608 WIRE -320 624 -336 624 WIRE -288 624 -288 608 WIRE -288 624 -320 624 WIRE -912 640 -912 560 WIRE -784 640 -784 608 WIRE -784 640 -912 640 WIRE -320 640 -320 624 WIRE -912 656 -912 640 WIRE -640 656 -640 544 WIRE -560 656 -640 656 WIRE -448 656 -480 656 WIRE -400 656 -448 656 WIRE -384 656 -384 560 WIRE -384 656 -400 656 WIRE 352 656 288 656 WIRE 464 656 464 608 WIRE 464 656 432 656 WIRE 480 656 464 656 WIRE 528 672 528 624 WIRE -448 688 -448 656 WIRE 288 688 288 656 WIRE 464 752 464 656 WIRE 480 752 464 752 WIRE -448 768 -448 752 WIRE 288 800 288 768 WIRE 528 800 528 768 WIRE 528 800 288 800 WIRE 528 944 528 800 WIRE 592 944 528 944 WIRE 720 944 592 944 WIRE 896 944 800 944 WIRE 1168 944 896 944 WIRE 1328 944 1248 944 WIRE 1328 1008 1328 944 WIRE 1328 1008 1264 1008 WIRE 528 1072 528 944 WIRE 832 1072 528 1072 WIRE 1328 1088 1328 1008 WIRE 832 1120 832 1072 WIRE 528 1136 528 1072 WIRE 1328 1184 1328 1152 WIRE 1328 1184 1264 1184 WIRE 1664 1200 1664 1152 WIRE 1664 1200 1632 1200 WIRE 1680 1200 1664 1200 WIRE 1328 1216 1328 1184 WIRE 1328 1216 1248 1216 WIRE 1248 1232 1248 1216 WIRE 1328 1232 1328 1216 WIRE 1408 1232 1328 1232 WIRE 1632 1232 1632 1200 WIRE 1632 1232 1504 1232 WIRE 1680 1232 1680 1200 WIRE 368 1248 304 1248 WIRE 464 1248 464 1216 WIRE 464 1248 448 1248 WIRE 480 1248 464 1248 WIRE 832 1248 832 1200 WIRE 304 1280 304 1248 WIRE 528 1280 528 1216 WIRE 1408 1312 1328 1312 WIRE 1632 1312 1504 1312 WIRE 1248 1344 1248 1312 WIRE 1328 1344 1328 1312 WIRE 1328 1344 1248 1344 WIRE 464 1360 464 1248 WIRE 480 1360 464 1360 WIRE 1632 1360 1632 1312 WIRE 1664 1360 1632 1360 WIRE 1680 1360 1680 1312 WIRE 1680 1360 1664 1360 WIRE 304 1392 304 1360 WIRE 528 1392 528 1376 WIRE 528 1392 304 1392 WIRE 608 1392 528 1392 WIRE 832 1392 832 1312 WIRE 832 1392 608 1392 WIRE 1328 1392 1328 1344 WIRE 1328 1392 832 1392 WIRE 1664 1392 1664 1360 WIRE 608 1456 608 1392 FLAG 208 528 0 FLAG 608 1456 0 FLAG 496 352 V_supply FLAG 1264 1008 Cres FLAG 592 944 FET_center FLAG 896 944 Lres FLAG -912 656 0 FLAG -960 256 0 FLAG -864 144 5V FLAG -624 320 2 FLAG -624 544 3 FLAG 464 608 upper_gate FLAG 464 1216 lower_gate FLAG -1008 432 test FLAG -448 496 0 FLAG -448 768 0 FLAG -320 416 0 FLAG -320 640 0 FLAG -400 384 2_delay FLAG -400 656 3_delay FLAG -96 336 2_out FLAG -112 560 3_out FLAG -1200 576 0 FLAG 1264 1184 V_R_Load_pri FLAG 1664 1392 0 FLAG 1664 1152 V_R_Load SYMBOL bv 288 672 R0 SYMATTR InstName B8 SYMATTR Value V=2*V(2_out) SYMBOL bv 304 1264 R0 SYMATTR InstName B9 SYMATTR Value V=2*V(3_out) SYMBOL res 448 640 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R3 SYMATTR Value 5R SYMBOL res 464 1232 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R4 SYMATTR Value 5R SYMBOL voltage 208 368 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V6 SYMATTR Value PULSE(0 48 1u 10u 1 10 20) SYMBOL res 288 336 M90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R11 SYMATTR Value 1m SYMBOL res 512 528 R0 SYMATTR InstName RS1 SYMATTR Value 1m SYMBOL res 512 1120 R0 SYMATTR InstName RS2 SYMATTR Value 1m SYMBOL res 1152 928 M90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName Rpri_sense SYMATTR Value 1m SYMBOL ind 704 928 M90 WINDOW 0 5 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName L_res SYMATTR Value 1.65µ SYMATTR SpiceLine Rser=1m SYMBOL cap 816 1248 R0 SYMATTR InstName C6 SYMATTR Value 220p SYMBOL res 816 1104 R0 SYMATTR InstName R15 SYMATTR Value 2R SYMBOL res 1664 1216 R0 SYMATTR InstName R_Load SYMATTR Value 30R SYMBOL cap 1344 1152 R180 WINDOW 0 24 56 Left 2 WINDOW 3 24 8 Left 2 SYMATTR InstName C_res SYMATTR Value 4.7n SYMBOL Comparators\\LT1719 -784 256 R0 SYMATTR InstName U1 SYMBOL Comparators\\LT1719 -784 480 R0 SYMATTR InstName U2 SYMBOL voltage -960 144 R0 SYMATTR InstName V1 SYMATTR Value 5V SYMBOL nmos 480 672 R0 SYMATTR InstName X1 SYMATTR Value IPD78CN10N_L1 SYMATTR Prefix X SYMBOL nmos 480 1280 R0 SYMATTR InstName X2 SYMATTR Value IPD78CN10N_L1 SYMATTR Prefix X SYMBOL res -480 368 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R2 SYMATTR Value 220R SYMBOL res -464 640 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R5 SYMATTR Value 220R SYMBOL cap -464 416 R0 SYMATTR InstName C3 SYMATTR Value 100p SYMBOL cap -464 688 R0 SYMATTR InstName C5 SYMATTR Value 100p SYMBOL Digital\\and -272 288 R0 WINDOW 3 -65 0 Left 2 WINDOW 123 16 52 Left 2 SYMATTR Value Vhigh=5 SYMATTR Value2 Trise=2n SYMATTR InstName A1 SYMBOL Digital\\and -272 512 R0 WINDOW 3 -55 -2 Left 2 WINDOW 123 16 52 Left 2 SYMATTR Value Vhigh=5 SYMATTR Value2 Trise=2n SYMATTR InstName A3 SYMBOL voltage -1200 448 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V3 SYMATTR Value SINE(0 1 1.84E6) SYMBOL ind 1392 1216 R0 SYMATTR InstName L1 SYMATTR Value 10m SYMATTR Type ind SYMATTR SpiceLine Rser=1m SYMBOL ind 1488 1216 R0 SYMATTR InstName L2 SYMATTR Value 90m SYMATTR Type ind SYMATTR SpiceLine Rser=1m SYMBOL res 1264 1328 R180 WINDOW 0 36 76 Left 2 WINDOW 3 36 40 Left 2 SYMATTR InstName R1000 SYMATTR Value 100Meg TEXT -1120 1112 Left 2 !.model pwr_diode D(Ron=1m Roff=1Meg Vfwd=.4) TEXT -1104 1072 Left 2 !.tran 0 0.6m 0.1m 10n TEXT -1120 1176 Left 2 !.model Sw_kw1 SW(Ron=.01 Roff=100Meg Vt=4 Vh=-1) TEXT -1184 -1144 Left 5 ;Fixed frequency Class D amplifier, 1.84Mhz, supply Volts = 48V, max power about 100W. TEXT 1400 1184 Left 2 !k1 L1 L2 1 TEXT 1400 1008 Left 3 ;power \ntransformer TEXT 1392 1088 Left 2 ;turns ratio is 1:3\nso inductance \nratio is 1:9 TEXT 1088 1432 Left 2 ;the resistance that appears at the transformer primary \nis R_Load/ turns ratio squared,\n= 45 Ohms/(3 squared) = 45/9 = 5 Ohms TEXT -1072 -512 Left 2 ;click on run\nthen click on "2_out" to plot its Voltage\nthen click on "3_out" to plot its Voltage \nZoom in on the time axis to see the individual pulses.\nthese signals turn on the upper FET then the lower FET, one at a time.\nclick on the plot window, then on plot settings/add plot pane.\nthen click on "FET_center" to plot its Voltage\n \nclick on the plot window, then on plot settings/add plot pane.\nthen click on "V_R_Load_pri" to plot its voltage\nnote that "FET_center" was a square wave, and that "V_R_Load_pri" is a sine wave.\nL_res and C_res resonate the frequency that we are driving the FETs at.\n \nthen click on "V_R_Load" to plot its Voltage.\nthe transformer has a turns ratio of 1:3, so "V_R_Load" is 3 times "V_R_Load_pri".\nclick on the plot window, then on plot settings/add plot pane.\nclick on the circuit, press and hold the alt key, hover the mouse over R_Load and click.\nthis will plot the power out.\npress and hold the CTRL key, in the graph window click on "V(V_R_Load)*I(R_Load)"\na window will appear giving average power out.\n \nclick on the plot window, then on "View /FFT" in the top toolbar, then on "V(v-r_load)"\nthis will plot its FFT. TEXT -1088 -592 Left 5 ;Instructions, first level TEXT 1960 -1176 Left 2 !**********\n.SUBCKT IPD78CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2.5n Ld=1n Lg=3n\n \n.PARAM Rs=3.14m Rg=0.8 Rd=50u Rm=660u\n.PARAM Inn=13 Unn=10 Rmax=78m gmin=6.5\n.PARAM act=1.238\n \nX1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} \n +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0\nRg g1 g {Rg} \nLg gate g1 {Lg*if(dgfs==99,0,1)}\nGs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)}\nRsa s1 s 1Meg\nLs source s1 {Ls*if(dgfs==99,0,1)}\nRda d1 d2 {Rd}\nLd drain d2 {Ld*if(dgfs==99,0,1)}\n \nE1 Tj w VALUE={TEMP}\nR1 w 0 1u\n.ENDS\n********** TEXT 1936 -560 Left 2 !.SUBCKT S3_100_a_var dd g s0 Tj PARAMS: a=1 dVth=0 dR=0 dgfs=0 Inn=1 Unn=1 Rmax=1\n+gmin=1 Rs=1 Rp=1 dC=0 Rm=1u heat=0\n \n.PARAM Fm=0.065 Fn=0.5 kbq=85.8u\n.PARAM c=1.55 muc=0.0 Vth0=4.073 auth=5.5m al=0.001\n.PARAM UT=100m ab=78.7m ab2=0 lB=-23 UB=132\n \n.PARAM b0=22.55 p0=6.62 p1=-20.6m p2=39.2u\n \n.PARAM Rd=60m nmu=2.75 Tref=298 T0=273 lnIsj=-25.7\n.PARAM ndi=1.17 Rdi=12m nmu2=0.3 ta=30n td=100n\n.PARAM Rf=0.34 nmu3=1.8 rpa=150u\n \n.PARAM f3=380p f3a=60p \n.PARAM ps1=45p ps2=-62.5m ps3=80p ps4=-2 ps5=1.06p ps6=4p\n.PARAM qs1=26p qs2=50p qs3=-2 qs4=175p qs5=-0.0357 \n \n.PARAM Vmin=3.073 Vmax=5.073 dCmax=0.33\n.PARAM Vth={Vth0+(Vmax-Vth0)*limit(dVth,0,1)-(Vmin-Vth0)*limit(dVth,-1,0)}\n.PARAM q0={b0*((T0/Tref)**nmu3)*a}\n.PARAM q1={(Unn-Inn*Rs-Vth0)*q0}\n.PARAM q2={(Fm*SQRT(0.4)-c)*Inn*q0}\n.PARAM Rlim={(q1+2*q2*Rmax-SQRT(q1**2+4*q2))/(2*q2)}\n.PARAM dRd={Rd/a+if(dVth==0,limit(dR,0,1)*max(Rlim-Rd/a-Rs-Rp,0),0)}\n.PARAM bm={c/((1/gmin-Rs)**2*Inn*a*(T0/Tref)**nmu3)}\n.PARAM bet={b0+(b0-bm)*if(dR==0,if(dVth==0,limit(dgfs,-1,0),0),0)}\n.PARAM dC1={1+dCmax*limit(dC,0,1)}\n \n.PARAM Cox1={ps1*a*dC1}\n.PARAM Cox2={ps3*a*dC1}\n.PARAM Cox3={(ps5*a+ps6)*dC1}\n.PARAM Cds0={qs1*a*dC1}\n.PARAM Cds1={qs2*a*dC1}\n.PARAM Cds2={qs4*a*dC1}\n.PARAM Cgs0={(f3a+f3*a)*dC1}\n.PARAM dRdi={Rdi/a}\n \n.FUNC I0(Uee,p,pp,z1,cc) {if(Uee>pp,(Uee-cc*z1)*z1,p*(pp-p)/cc*exp((Uee-pp)/p))}\n.FUNC Ig(Uds,T,p,Uee,cc) {bet*(T0/T)**nmu3*I0(Uee,p,min(2*p,p+cc*Uds),min(Uds,Uee/(2*cc)),cc)}\n.FUNC J(d,g,T,da,s) \n+ {a*s*((Ig(da,T,(p0+(p1+p2*T)*T)*kbq*T,g-Vth+auth*(T-Tref)+Fm*da**Fn,c*(T/Tref)**muc)+exp(min(lB+(d-UB-ab*(T-Tref))/UT,25))))}\n \n.FUNC Idiode(Usd,Tj,Iss) {exp(min(log(Iss)+Usd/(ndi*kbq*Tj),7))-Iss}\n.FUNC Idiod(Usd,Tj) {a*Idiode(Usd,Tj,exp(min(lnIsj+(Tj/Tref-1)*1.12/(ndi*kbq*Tj),7))*(Tj/Tref)**3)}\n \nE_Edg1 d ox VALUE {if(V(d,g)>0,V(d,g)-(exp(ps2*max(V(d,g),0))-1)/ps2,0)}\nC_Cdg1 ox g {Cox1}\nE_Edg2 d ox1 VALUE {if(V(d,g)>0,V(d,g)-(exp(ps4*max(V(d,g),0))-1)/ps4,0)}\nC_Cdg2 ox1 g {Cox2}\nVx d ox2 0\nC_Cdg3 ox2 g {Cox3}\n \nE_Eds d edep VALUE {(V(d,s)-I(V_sense3)/(Cds0+Cds1+Cds2))}\nC_Cds edep s {Cds0+Cds1+Cds2}\n \nC_Cgs g s {Cgs0}\n \nG_chan d s VALUE={J(V(d,s),V(g,s),T0+limit(V(Tj),-200,300),(SQRT(1+4*al*abs(V(d,s)))-1)/2/al,sgn(V(d,s)))}\nG_RMos d1 d VALUE={V(d1,d)/(Rf*dRd+(1-Rf)*dRd*((limit(V(Tj),-200,999)+T0)/Tref)**nmu)/(1+rpa*(I(V_sense)/a)**2)}\nV_sense dd d1 0\nG_diode s d3 VALUE={Idiod(V(s,d3),T0+limit(V(Tj),-200,499))}\nG_Rdio d2 d1 VALUE={V(d2,d1)/(dRdi*((limit(V(Tj),-200,999)+T0)/Tref)**nmu2)}\nV_sense2 d2 d3 0\n \nL_L001 a c {td/(ta+td)}\nR_R001 a b {1/ta}\nV_sense3 c 0 0\nE_E001 b 0 VALUE {I(V_sense2)}\nE_E002 e 0 VALUE {Cds1/qs3*(exp(qs3*max(V(d1,s),-1))-1)+Cds2/qs5*(exp(qs5*max(V(d1,s),-1))-1)+Cds0*V(d1,s)} \n \nR_R002 e c 1\nR_R003 a 0 500Meg\n \nR1 g s 1G\nRd01 d s 500Meg\nRd02 d2 s 500Meg\nRd03 d1 d 1k\n \nRmet s s0 {Rm}\n \nG_TH 0 Tj VALUE =\n+{(LIMIT(I(V_sense2)*V(d1,s)+(V(s,s0)**2)/Rm+(I(V_sense)-I(V_sense2))*V(d1,d)+\n+(I(V_sense)-I(V_sense2)-I(E_Edg1)-I(E_Edg2)-I(Vx)-I(E_Eds))*V(d,s),-10k,100k))}\n \n.ENDS\n \n********* TEXT 616 832 Left 2 ;with 1.84Mhz and 4.7nF \nL would be 1.592uH for resonance\nL increased to 1.65uH to cause reduced loss switching TEXT 304 -384 Left 2 ;resonance occurs at the 1.84Mhz driving frequency when\nC_res = 4.7nH and L_res = 1.592uH,\nHowever, if we operate with these values we get lossy switching of the FETs\nefficiency calculated as.... (power in R_load) / (48V x I(R_sense_in))\n= 133.9W out / (48V x 2.862A) input = 133.9W / 137.4W = 97.5%\n \nif we increase the value of the inductor to 1.65uH \nefficiency increases to 99.1%, this is due to reduced loss switching in the FETs.\nwe achieve this by having a "deadtime" after one FET is turned off and before the other FET is turned on.\nwe then have to arrange the resonant current so that it charges the output capacitance of the FETs, \nduring the deadtime, this causes the voltage across the FET which is about to turn on, to reduce to zero \nbefore it turns on.\n \na couple of details here.\nThe efficiency figures here ignore several losses such as those in the inductor and transformer.\nHence you will not achieve such high efficiency in a real circuit.\nnote that the LTspice power dissipation function (achieved by pressing the alt key and hovering the mouse over the component),\ndoes not function well for a complex component such as a FET. It works okay for a resistor though. TEXT 368 -440 Left 5 ;Instructions, reducing switching losses. TEXT -1192 -1000 Left 4 ;Using an infineon silicon FET, a lower current rating FET is chosen, to keep FET output capacitance low, so that fast switching is possible.\nHowever the FET should still be adequately derated.\nthe resonant inductor will be wound on a core rather than being air cored. \nDue to the low frequency the inductor value is too high for available air cored components, and magnetic core materials are available \neg MPP powder cores from Mag-inc., and 3F4, 3F46, and 4F1, Ferrite materials from Ferroxcube.\nmax frequencies are about up to 2 Mhz (MPP), and perhaps 5Mhz for the highest freq. power ferrites.\nsome ferroxcube 3F46 material cores available from digikey. TEXT -1120 1608 Left 2 ;You may republish or reuse this circuit implementation and text providing this line and the following lines are included.\nThis circuit implementation designed by Keith Wallbanks. Originally released on analogsimulation.co.uk\nThis circuit is provided as is without warranty of any kind. This text is intended to implement the MIT licence.# TEXT 1920 -1256 Left 3 ;The below is one of Infineons Spice models for this FET.\nOther Spice models for this FET exist on the Infineon website. RECTANGLE Normal 1600 1344 1360 976 2