Version 4.1
SHEET 1 2100 680
WIRE 32 80 -320 80
WIRE 128 80 32 80
WIRE 336 80 128 80
WIRE 336 112 336 80
WIRE -320 144 -320 80
WIRE 128 176 128 80
WIRE 336 224 336 192
WIRE 400 224 336 224
WIRE 480 224 400 224
WIRE 768 224 544 224
WIRE 784 224 768 224
WIRE 336 240 336 224
WIRE -144 288 -192 288
WIRE -64 288 -144 288
WIRE 128 288 128 256
WIRE 128 288 0 288
WIRE 176 288 128 288
WIRE 272 288 176 288
WIRE 336 352 336 336
WIRE 384 352 336 352
WIRE 528 352 384 352
WIRE 768 352 768 224
WIRE 336 368 336 352
WIRE 128 416 128 288
WIRE -192 432 -192 288
WIRE 336 464 336 448
WIRE 528 464 336 464
WIRE 336 480 336 464
WIRE 528 480 528 464
WIRE -320 592 -320 224
WIRE -192 592 -192 512
WIRE -192 592 -320 592
WIRE 128 592 128 496
WIRE 128 592 -192 592
WIRE 256 592 128 592
WIRE 336 592 336 560
WIRE 336 592 256 592
WIRE 528 592 528 544
WIRE 528 592 336 592
WIRE 768 592 768 432
WIRE 768 592 528 592
WIRE 848 592 768 592
WIRE 256 640 256 592
FLAG 784 224 out
FLAG -144 288 input
FLAG 32 80 Vsupply
FLAG 256 640 0
FLAG 176 288 base
FLAG 400 224 collector
FLAG 384 352 emmitter
SYMBOL res 112 160 R0
SYMATTR InstName R1
SYMATTR Value 12k
SYMBOL npn 272 240 R0
SYMATTR InstName Q1
SYMATTR Value 2N2222
SYMBOL res 112 400 R0
SYMATTR InstName R2
SYMATTR Value 1.2k
SYMBOL cap 0 272 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 100n
SYMBOL cap 544 208 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 100n
SYMBOL res 320 96 R0
SYMATTR InstName R_collector
SYMATTR Value 1.4k
SYMBOL res 320 464 R0
SYMATTR InstName R_emmitter_1
SYMATTR Value 90
SYMBOL voltage -320 128 R0
SYMATTR InstName V1_supply
SYMATTR Value 15V
SYMBOL voltage -192 416 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 0.01 100k)
SYMBOL res 752 336 R0
SYMATTR InstName R3
SYMATTR Value 1Meg
SYMBOL cap 512 480 R0
SYMATTR InstName C_emmitter
SYMATTR Value 1µ
SYMBOL res 320 352 R0
SYMATTR InstName R_emmitter_2
SYMATTR Value 30
TEXT -296 -352 Left 5 ;Common emmitter amplifier, for Voltage gain.
TEXT -288 624 Left 2 !.tran 0.4m
TEXT -392 -256 Left 4 ;instructions
TEXT -392 -216 Left 2 ;click on run\nthen click on "input" to plot it.\nthen click on the plot window, then on plot settings/add plot pane\nthen click on "base" to plot it\nthen click on the plot window, then on plot settings/add plot pane\nthen click on "collector" to plot it\nthen click on the plot window, then on plot settings/add plot pane\nthen click on "output" to plot it
TEXT 680 472 Left 2 ;R3 is to give the node "out"\na DC path to ground.\nSpice simulators require this.
TEXT 616 -240 Left 4 ;Circuit Description
TEXT 432 -200 Left 2 ;R_emmitter_1 is split into two parts and R_emmitter_1 is \nAC bypassed to increase AC gain.\nThe Voltage gain of this cct is approximately calculated as \nR_collector/R_emmitter_2 = 1.4k/30R = 46.6\nhowever the internal transistor emmitter resistance reduces \nthe gain, giving a gain of 40.\nsee the document "cm emmitter design proc" for more detail.
TEXT -304 -304 Left 3 ;See the following doc "common emmitter design proedure for more detail.
TEXT 384 624 Left 0 ;You may republish or reuse this circuit implementation and text providing this line and the following lines are included.\nThis circuit implementation designed by Keith Wallbanks., Originally released on analogsimulation.co.uk\nThis circuit is provided as is without warranty of any kind. This text is intended to implement the MIT licence.